Peripheral Simulation

For STMicroelectronics STR730FZ2 — Pulse Width Modulators (PWM0-PWM5)

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

Pulse Width Modulation Dialog

The Pulse Width Modulator dialog configures Pulse Width Modulator (PWM) simulation.

Prescalers

• PWM0_PRS0 (PWM Prescaler 0) contains the divider factor (1, 2, 4, 8,..., 128) applied to the input clock.
• PR0 (Prescaler Register 0) selects the value (0-7) that corresponds to the primary divider factor (0=1, 1=2, 2=4, 3=8,..., 7=128).
• PWM0_PRS1 (PWM Prescaler 1) contains the divider factor (1-32)applied to the output of the the first prescaler.
• PR1 (Prescaler Register 1) selects the value (0-31) that corresponds to the secondary divider factor.

Enable & Polarity Interrupt

• PWM0_PEN (PWM Enable Register) contains the PWM Enable Register contents.
• PE (PWM Enable) is set to enable the PWM.
• PWM0_PLS (PWM Output Polarity Selection Register) controls the polarity (inverted or not inverted) of the PWM output.
• PL (PWM Polarity) is set to invert the PWM output.
• PWM0_CPI (PWM Compare Period Interrupt Register) contains the Compare Period Interrupt bit (CP) bit.
• CP (PWM Compare Period) is set to indicate that the compare register value has been reached.
• PWM0_IM (PWM Interrupt Mask Register) contains the Compare Period Interrupt Mask bit (IM) bit.
• IM (PWM Interrupt Mask) is set to enable the PWM interrupt.

Output Duty & Output Period

• PWM0_DUT (PWM Output Duty Register) contains the number of clocks that the output signal is at a high level, or low if polarity is inverted.
• PWM0_PER (PWM Output Period Register) contains the number of clocks that define the length of the entire PWM cycle.