Peripheral Simulation

For STMicroelectronics STM32F103ZD — APB Bridge 2

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

APB Bridge 2 Dialog

The APB Bridge 2 dialog configures the low-power, APB Bridge of the STR7x device. This bridge interfaces the system peripherals and the interrupt controller.

Selected Peripheral

• Peripheral Clock Disable  is checked to disable the peripheral clock for the selected peripheral.
• Peripheral Reset  is checked to reset the selected peripheral.

Clock Disable & Software Reset

• APB2_CKDIS (APB Clock Disable Register) contains the peripheral clock disable bit settings.
• APB2_SWRES (APB Software Reset Register) controls the reset of the APB 2 peripherals.